Intel’s EMIB-T takes aim at TSMC’s CoWoS-L as AI chip packaging gets crowded

Intel is pitching its bridge-based packaging as a higher-yield, lower-cost alternative while TSMC's CoWoS capacity stays fully booked Intel wants a bigger piece of the AI chip boom, and it is not starting with the chips themselves. It is starting with the packaging that holds them together. The company expects future AI packages to carry more than 32 HBM stacks and over 70 EMIB bridges. That is a lot of hardware crammed into one slab, and Intel is betting its EMIB-T technology can handle it more efficiently than TSMC’s CoWoS-L. What Intel is actually selling TSMC’s CoWoS approach has historically leaned on a large silicon interposer, essentially a big slab of silicon that everything sits on. CoWoS-L, the version in question, is the variant now drawing direct comparisons with Intel’s offering. Intel’s EMIB-T takes a different route. Instead of one giant silicon foundation, it embeds small, localized silicon bridges inside an organic substrate, placing silicon only where chips need to talk to each other. The “T” adds through-silicon vias (TSVs), which are vertical electrical connections running through the bridge. Put simply, they give power a more direct path into the package, which...